The present invention relates to heterogeneous computer architectures employing multiple processor types (for example, CPUs and GPUs) and, in particular, to a memory controller providing improved access to common memory when a single parallel application is divided among heterogeneous processors.
Modern computer systems may provide heterogeneous processor architectures, for example, employing one or more conventional computer processing units (CPUs) operating in tandem with specialized graphical processing units (GPUs) the latter tailored to a high-speed streaming processing. Such systems can be performance limited by the speed of off-chip memory access.
One method of improving the speed of offchip memory access in such systems is to provide access priority to CPU cores. This priority reflects a general understanding that the CPU cores represent a relatively small proportion of memory accesses (minimizing their overall impact on GPU memory accesses) and that CPU cores are less able to tolerate long memory access latency. In contrast GPUs can offset long memory access latency by implementing a large number of hardware threads.
Deciding how to prioritize memory access for one processor type in a heterogeneous processor architecture is difficult because of the unknown relative importance of each task with respect to system performance. Accordingly such systems rely heavily on preserving “fairness” in the allocation; that is, priority systems in which each processor type is guaranteed a given minimum amount of memory access.